Inductors and transformers are used in a wide variety of integrated circuit applications including radio frequency (RF) integrated circuit applications. An on-chip inductor is a passive electrical component that can store energy in a magnetic field created by the current passing through it. An inductor can be a conductor shaped as a coil which includes one or more “turns.” The turns concentrate the magnetic field flux induced by current flowing through each turn of the conductor in an “inductive” area within the inductor turns. The number of turns and the size of the turns affect the inductance.
Two (or more) inductors which have coupled magnetic flux form a transformer. A transformer is a device that transfers electrical energy from one circuit to another through inductively coupled conductors, usually the coils or turns of the inductors that form the transformer. A varying current in a first or “primary” inductor induces a varying voltage in a second or “secondary” inductor. If a load is coupled to the secondary inductor, a current will flow in the secondary inductor and electrical energy will flow from the primary circuit through the transformer to the load.
Conventional inductors implemented in integrated circuit dies and circuit packages can have several drawbacks. These inductors can be made by forming helical or spiral traces in conductive layers to form inductor turns. In some cases, these traces may be coupled to traces in adjacent layers in order to achieve higher inductance. Unfortunately, the inductors can consume excessive metal layer resources and may not provide sufficient current capacity or high enough quality factor without undesirable scaling. In addition, because the inductive areas of the inductors are substantially parallel with respect to other trace layers in the package substrate and circuit die, they can have unfavorable electromagnetic interference (EMI) effects on other components within the integrated circuit and/or their inductor characteristics can be adversely affected by adjacent conductors within the substrate or circuit die.
FIG. 1 shows a cross-section of CMOS technology 100 which includes three sections: a Redistributed Design Layer (RDL) section 102, a Front-End-Of-the-Line (FEOL) section 104, and a Back-End-Of-the-Line (BEOL) section 106. The FEOL section 104 includes a substrate 108 and the BEOL section 106 includes a plurality of metal layers M1-Mn. The height or thickness 114 of the FEOL section 104 is usually much greater than the height or thickness 110 of the BEOL section 106. The metal layers of the BEOL section 106 that are close to the substrate 108 are used for interconnections between devices, and conventional inductors can induce undesired coupling to surrounding layers. Thus, to provide space for interconnections and to minimize undesired coupling caused by conventional inductors, an inductor available height 112 in the BEOL section 106 away from the substrate 108 is less than the total height 110 of the BEOL section 106. Conventionally, on-chip inductors are usually fabricated using a two-dimensional geometry in one or more of the metal layers M1-Mn in the BEOL section 106.
A top-view of an exemplary symmetrical one-turn inductor 200 having two input ports 202, 204 is illustrated in FIG. 2. The symmetrical inductor 200 can be split by a symmetry line 206 such that a first half of the inductor 208 on one side of the symmetry line 206 has the same dimensions as a second half of the inductor 210 on the other side of the symmetry line 206. However, since the inductance value is proportional to the total length of the metal line used to form the inductor, the one-turn inductor geometry of the symmetrical inductor 200 has an inductance disadvantage because it only has a single turn. Additional turns or metal length can increase the inductance value.
The dimension ratio between a conventional on-chip inductor and a transistor can provide an appreciation of the relatively excessive metal layer resources that can be consumed by an inductor in a BEOL metal layer. A conventional on-chip inductor can take up a 300 μm×300 μm or an area of 90,000 μm2. In contrast, using an available feature size, a transistor can take up an area of 0.09 μm2. Thus, the chip size ratio between the space consumed by the inductor and the transistor is 1,000,000:1. In addition, due to CMOS technology scaling, the chip cost per mm2 continues to increase because the BEOL for passive devices does not scale while the FEOL for active devices does scale. Thus, the chip cost of an inductor or transformer is very high and is likely to increase in more advanced technology nodes, for example 45 nm or 32 nm.
A top-view of an exemplary spiral multi-turn inductor 300 is illustrated in FIG. 3. The spiral architecture can be used to increase the inductance value. The spiral multi-turn inductor 300 does not have symmetry like the one-turn inductor 200 but it has an increased inductance value due to the increased total series metal length. The lack of symmetry gives the inputs of the inductor 300 polarity. Since the inductance value of the inductor 300 is proportional to the total series metal length used to form the inductor 300, the inductance value is affected by the width of the metal conductor forming the inductor turns, the space between the turns, the diameter of the metal conductor and the number of turns in the spiral. The inputs to the inductor 300 are usually brought out to the same side of the inductor structure. The spiral multi-turn inductor 300 includes a multi-turn spiral portion 302, a first input 304 and a second input 306 which is brought out from the spiral ending point 308 to the same side of the inductor 300 as the first input 304. A lead 310 is used to bring the second input 306 out from the spiral ending point 308 of the inductor 300. In this configuration, the multi-turn inductor 300 has some disadvantages versus the one-turn inductor 200. The multi-turn inductor 300 needs two metal layers: one metal layer for the first input 304 and the spiral portion 302 to increase inductance; and a second metal layer for the lead 310 to bring the second input 306 out from the spiral ending point 308. In contrast, the one-turn inductor 200 can be implemented on one metal layer. The spiral multi-turn inductor 300 also has overlap regions 312 and 314 due to its multi-turn portion 302 crossing the lead 310 which can cause capacitive coupling between the layers. These capacitive coupling of these overlap regions 312, 314 can degrade the performance of the inductor 300.
Since the metal layers M1-Mn are also used for interconnections between devices and other purposes than making inductors, such as inductors 200 and 300, the inductor available height 112 is less than the total height 110 of the BEOL section 106. These types of inductors will also induce undesired coupling to surrounding layers. To lower coupling to the substrate these types of inductors are usually put in the upper metal layers. In addition, other devices or interconnections on the same metal layer as the inductors 200 or 300 are separated from the inductor by an isolation distance, for example 100 microns, to prevent magnetic coupling between the inductor and the other devices or interconnections. This isolation distance is determined by the required isolation of circuits from the inductors magnetic field, and adds to the area consumed by the inductor, and thus increases the cost of the die.
A conventional method to further increase the total metal length of an inductor is metal series stacking. FIG. 4 illustrates an inductor 400 that includes three different metal layers 402, 404, 406 that are formed in the metal layers M1-Mn of the BEOL section 106. The metal layers 402 and 404 are separated by a distance 412, and the metal layers 404 and 406 are separated by a distance 414. The metal layers 402, 404, 406 are connected in series by vertical connectors 408 and 410. The three-layer inductor 400 has a first input 416 on the metal layer 402 and a second input 418 on the metal layer 406. The second input 418 may be brought out to the same side of the inductor structure as the first input 416 using a metal lead on another layer similar to the lead 310 shown in FIG. 3. The distances 412, 414 between the metal layers 402, 404, 406 are very small (for example 2-3 μm) relative to the diameter of the spiral shapes (for example 200 μm) on each of the metal layers 402, 404, 406. Thus, the lengths of the vertical connectors 408 and 410 contribute only a negligible amount to the overall inductor length. The total metal length of the inductor 400 is approximately 3 times greater than the total metal length of the inductor 300. However, the three layer inductor 400 conventionally has an inductance value that is less than 3 times greater than the inductance value of the inductor 300 because the total inductance is decreased due to magnetic field cancellation between the multiple layers. Thus, the ability to increase the inductance value using metal stacking is limited due to process constraints for the BEOL section 106.
Note that for any of the above inductor configurations, the inductance is a function of the total metal conductor length. Thus the inductor size is the same regardless of the technology. Each metal layer used for these inductors could alternatively provide space for billions or more transistors. In addition, because the inductive areas of the inductors are substantially parallel with respect to other trace layers, they can have unfavorable electromagnetic interference (EMI) effects on other components within the integrated circuit and/or their inductor characteristics can be adversely affected by adjacent conductors.
These issues for inductors are multiplied in the case of transformers which are made up of two or more inductors. An exemplary implementation of a transformer 500 in the BEOL section of a chip is illustrated in FIG. 5. The chip includes a BEOL section 502, where the transformer 500 is implemented, and a FEOL section 504. The FEOL section 504 includes the substrate 506 and various upper layers deposited on top of the substrate 506 for doping and other purposes where the active devices of the chip are usually located. The transformer 500 includes a first inductor 510 and a second inductor 512 that are inductively coupled. In this implementation, the metal layers in the BEOL section 502 get progressively thicker to tune the inductance values of the first inductor 512 and the second inductor 512. For clarity, the right-hand side of FIG. 5 shows a symbolic representation of the transformer 500. The first inductor 510 has a first input P1 for connection to a circuit on the chip and a second input coupled to ground. The second inductor 512 has a first input P2 for connection to another circuit on the chip and a second input that is also coupled to ground. The symbolic representation also illustrates the inductive coupling in the transformer 500 between the first inductor 510 and the second inductor 512. Similar to the inductors illustrated above, this transformer implementation consumes a significant amount of area which is very costly.
Thus, it would be desirable to have a new type of inductor for use in transformers and integrated circuits that can create higher inductance values in less space, that can take advantage of smaller feature size advancements, or that has less electromagnetic interference effects on other components within the integrated circuit.